Digital System Design using FSMs. Peter D. Minns

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      11 Appendix A4Figure A4.1 State diagram for single/multiple‐pulse generator with memory FS...Listing A4.1 Single‐pulse multi‐pulse generator.Listing A4.2 The test bench module.Figure A4.2 Verilog HDL simulation of its operation as Listing A4.2.Listing A4.3 Memory tester ‐ behavioural mode.Figure A4.3 Verilog HDL simulation of Listing A4.3.

      12 Appendix A5Figure A5.1 Diagram of the system for the programmable FSM.Figure A5.2 The parallel loading up counter and its inputs and outputs.Figure A5.3 The operation of an eight‐input multiplexer.Figure A5.4 The operation of an eight‐bit memory device.Figure A5.5 The instruction set for the programmable FSM.Figure A5.6 Shows how the IBF instruction can be implemented.Figure A5.7 Example of a single‐pulse FSM using the instruction set.Figure A5.8 The main circuit diagram for the programmable single‐pulse FSM....Figure A5.9 The state diagram for the motor with fault programmable FSM with...Figure A5.10 Main circuit diagram for the programmable motor with fault FSM....Figure A5.11 The program sequence for the motor with fault FSM.

      13 Appendix A6Figure A6.1 The m and s waveforms produced by the optical detector. Source: ...Figure A6.2 State diagram for the rotational detector FSM. Source: D. Zissos...Figure A6.3 Circuit for the Logisim rotational detector – note sub‐circuit f...Figure A6.4 Circuit for Logisim m and s optical detectorFigure A6.5 Alternative state diagram for the rotational detector.

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