Digital System Design using FSMs. Peter D. Minns

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      1 Appendix A3Table A3.1 The binary down counter.

      1 Chapter 1Figure 1.1 Block diagram of an FSM‐based application.Figure 1.2 Block diagram with five inputs and two outputs.Figure 1.3 Block diagram of a Mealy state machine structure.Figure 1.4 Block diagram of a Moore state machine structure.Figure 1.5 Block diagram of a Class C state machine structure.Figure 1.6 Transition between states.Figure 1.7 Transition with and without outside world inputs.Figure 1.8 Outside world input between states.Figure 1.9 Placement of outside world outputs.Figure 1.10 The block diagram for the state diagram shown in Figure 1.9.Figure 1.11 Block diagram of single pulse with memory FSM.Figure 1.12 State diagram for single pulse with memory FSM.Figure 1.13 State diagram for single‐pulse generator with memory and dummy s...Figure 1.14 Block diagram for the FSM.Figure 1.15 State diagram of single‐pulse generator with a multipulse featur...Figure 1.16 Block diagram showing secondary state variables in the FSM.Figure 1.17 State diagram with Mealy output P.Figure 1.18 Timing diagram showing Moore and Mealy outputs.Figure 1.19 Development of a 101 pattern generator sequence.Figure 1.20 Complete state diagram for the 101 pattern generator.Figure 1.21 Modified state diagram with output P as a Mealy output.Figure 1.22 State diagram with Mealy P output in s3.Figure 1.23 Timing diagram showing the effect of input x on output P.

      2 Chapter 2Figure 2.1 A timing module.Figure 2.2 Wait state sequence to control the timing module.Figure 2.3 Block diagram showing how to use the timing module with an RC tim...Figure 2.4 State diagram showing how to use the timing module.Figure 2.5 Block diagram controlling an ADC from a state diagram.Figure 2.6 Block diagram for a small DAS.Figure 2.7 Control of a memory device note negating circles at /CS,/W,/R.Figure 2.8 Timing of the control of a memory device.Figure 2.9 T1 to T4 timing stages.Figure 2.10 Using FSM to control the writing of data to a memory device.Figure 2.11 State diagram of the DAS.Figure 2.12a Block diagram for the two D detector FSM.Figure 2.12b State diagram to detect d twice.Figure 2.13 Block diagram to detect a 1010 sequence.Figure 2.14 Timing diagram showing the 1010 d input and its effect on the P ...Figure 2.15 A 110 sequence detector FSM.Figure 2.16 A possible 110 detector attempt.

      3 Chapter 3Figure 3.1 T type flip‐flop using exclusive OR and a D type flip‐flop.Figure 3.2 State diagram for the single‐pulse generator with memory having M...Figure 3.3 A different state diagram using T type flip‐flops.Figure 3.4 Repeated diagram.Figure 3.5 D type flip‐flop with its characteristics.Figure 3.6 Timing showing behaviour of D type flip‐flop.Figure 3.7 The effect of a glitch.Figure 3.8 A complete example.Figure 3.9 State diagram with single/multiple‐pulse FSM.Figure 3.10 State diagram of Figure 3.9 again.Figure 3.11 Different ABCD transitions in a two‐way branch.Figure 3.12 Some more examples to try.Figure 3.13 A state diagram with two two‐way branches.Figure 3.14 The effect of asynchronous and synchronous resets.Figure 3.15 Complete design circuit for the FSM.Figure 3.16 Repeat of completed circuit showing P output with and without cl...Figure 3.17 This example has an x input for Mealy output L.Figure 3.18 Use this to complete the design equations.Figure 3.19 The circuit with lower AND gate to allow reset of flip‐flop B.Figure 3.20 The effect of Moore/Mealy outputs for P and L.Figure 3.21 CS and W outputs using De‐Morgan’s rule.Figure 3.22 How W and R are used.Figure 3.23 Block diagram of the binary data serial transmitter.Figure 3.24 State diagram for binary data serial transmitter.Figure 3.25 With additional dummy state s7.Figure 3.26 Simulation of the binary data serial transmitter.Figure 3.27 The high low FSM system.Figure 3.28 State diagram of the high‐low system.Figure 3.29 Simulation of the high‐low system.Figure 3.30 The clocked watchdog timer.Figure 3.31 State diagram of the watchdog timer.Figure 3.32 Simulation of the watchdog timer.Figure 3.33 Data packet protocol.Figure СКАЧАТЬ