Multi-Processor System-on-Chip 2. Liliana Andrade
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Название: Multi-Processor System-on-Chip 2
Автор: Liliana Andrade
Издательство: John Wiley & Sons Limited
Жанр: Зарубежная компьютерная литература
isbn: 9781119818403
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MPSoC started a new computing era, but brought a twofold challenge: building multi-core HW that can be used easily by SW designers, and building distributed SW that fully exploits HW capabilities. To deal with these challenges, the design communities from Academia and Industry began a series of conferences and workshops to rethink classical distributed computing. The study of new methods, models and tools to deal with these new distributed HW and SW architectures generated new concepts, such as the interconnect architectures called network-on-chip (NoC). The MPSoC Forum, created in 2001, was the first interdisciplinary forum that brought together the leading thinkers from the different fields to design multi-core and multi-processor SoC. Over the last 20 years, MPSoC was a unique opportunity for me to meet so many of the world’s top researchers and to communicate with them in person, in addition to enjoying the high-quality conference programs. The confluence of academic and industrial perspectives, and hardware and software, makes MPSoC not “yet another conference”. I have learned how emerging SW and HW design technologies and architectures can benefit from advanced semiconductor manufacturing technologies to build energy-efficient multi-core architectures that can serve advanced computing (image, vision and cloud) and distributed networked systems. This book, in two volumes (Architectures and Applications), was published to celebrate the 20th anniversary of MPSoC with outstanding contributions from previous MPSoC events.
This first volume on architectures covers the key components of MPSoC: processors, memory, interconnect and interfaces.
Acknowledgments
Liliana ANDRADE and Frédéric ROUSSEAU
Université Grenoble Alpes, CNRS, Grenoble INP, TIMA, 38000 Grenoble, France
The editors are indebted to the MPSoC community who made this book possible. First of all, they acknowledge the societies that supported this project. EDAA and IEEE/CAS partially funded the organization of the first two events. Since its creation, IEEE/CEDA has sponsored the event. Industrial sponsors played a vital role in keeping MPSoC alive for the last 20 years; special thanks to Synopsys, Arteris, ARM, XILINX and Socionext. The event was created by a nucleus of several people who now form the steering committee (Ahmed Jerraya, Hannu Tenhunen, Marilyn Wolf, Masaharu Imai and Hiroto Yasuura). A larger group has, for the last 20 years, been working to form the community (Nicolas Ventroux, Jishen Zhao, Tsuyoshi Isshiki, Frédéric Rousseau, Anca Molnos, Gabriela Nicolescu, Hiroyuki Tomiyama, Masaaki Kondo, Hiroki Matsutani, Tohru Ishihara, Pierre-Emmanuel Gaillardon, Yoshinori Takeuchi, Tom Becnel, Frédéric Pétrot, Yuan Xie, Koji Inoue, Masaaki Kondo, Hideki Takase and Raphaël David). The editors would like to acknowledge the outstanding contribution of the MPSoC speakers, and especially those who contributed to the chapters of this book. Finally, the editors would like to thank the people who participated in the careful reading of this book (Breytner Fernandez and Bruno Ferres).
1
From Challenges to Hardware Requirements for Wireless Communications Reaching 6G
Stefan A. DAMJANCEVIC1, Emil MATUS1, Dmitry UTYANSKY2, Pieter VAN DER WOLF3 and Gerhard P. FETTWEIS1, 4
1 Vodafone Chair Mobile, Communications Systems, TU Dresden, Germany
2 Synopsys, Saint Petersburg, Russia
3 Solutions Group, Synopsys, Inc., Eindhoven, The Netherlands
4 Barkhausen Institut, TU Dresden, Germany
Over the past few decades, we have seen rapid innovation in wireless communications. In particular, the IEEE 802.11 and 3GPP standardization organizations have driven data rates into the Gb/s range, enabling modern life, at home, at work and on the road. Societies of today have become dependent on this important infrastructure. The basis of this development is an infrastructure based on electronic circuits, which are driven, at heart, by very advanced multi-processor system-on-chip engines.
Firstly, we want to deliver a vision on what is to be expected from 6G, the next innovation wave of cellular technology. Cellular 1G was about delivering analogue voices, and digital 2G fixed it. The intention of 3G was to deliver data, but only 4G made it proficiently available for the service requirements. With 5G, we see the advent of the Tactile Internet, i.e. connecting remote controls not as point-to-point solutions but via a network. Will 6G be just a “fix” of issues left unsolved? We believe 6G will deliver truly more than this, and will also require many more sophisticated signal processing tasks.
Secondly, we want to analyze the computational tasks of 5G and beyond baseband processing, as well as their specification requirements. It becomes clear that the heterogeneity of computation cannot be mapped efficiently onto a homogeneous processor array. Instead, we need to find the right architecture for the right task. The reader is introduced to an extremely varied set of requirements as the services dramatically differ in terms of latency, data rate and reliability.
Thirdly, we want to give perspective and a sense of scale required from hardware for the previously determined corner workloads. We do this by implementing an example beyond 5G algorithm generalized frequency division multiplexing, with regard to those workloads, on a prototype software programmable single-instruction, multiple-data wide vector processing machine. Workloads alone are not sufficient to deduce adequate requirements for hardware (HW). To bridge the gap between workloads and HW requirements, we need to know how the 6G candidate waveform modulation translates workloads into HW requirements.
Conclusively, the performance–cost analysis shows a need for high flexibility. The low-end use case of the implemented algorithm easily fits within one 1 GHz 512 bit vector processor core requiring 1.01 − 5.39 MHz of the processor clock budget, therefore enabling seamless time multiplexing with other software (SW) kernels running on the core. The carrier aggregation (CA) high-end use case requires 921 − 5,505 MHz, which allows the prior clock-efficient version to fit on one 1 GHz 512 bit vector processor core. This sets the stage for the system designer to opt between a generalized vector processor or some more specialized HW accelerator engine, such as a dedicated (application-specific) HW accelerator or an application-specific instruction set processor (ASIP). Finally, the implemented algorithm running the multiple-input, multiple-output (MIMO) CA high-end use case would require a budget of 7.37 − 44.04 GHz, the theoretical equivalent of eight or forty-five 512 bit vector processor cores, making the high-end use case more suitable for execution on the dedicated HW accelerator or the ASIP, which were otherwise powered down. The use case corners demonstrate a high variability requirement from HW, which makes heterogeneous multi-processor system-on-chip (MPSoC) solutions ideal future-proof HW for beyond 5G. In this chapter, we present our key findings that connect the dots from vision to future HW in wireless communications.
1.1. Introduction
As we are writing this chapter СКАЧАТЬ