Multi-Processor System-on-Chip 2. Liliana Andrade
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      Liliana ANDRADE

      I express my profound gratitude to Karine, my parents and all my family, for their help and support throughout all these years.

      Frédéric ROUSSEAU

      Electronics Engineering, Field Director – Francis Balestra

      Design Methodologies and Architecture, Subject Head – Ahmed Jerraya

      Multi-Processor System-on-Chip 2

       Applications

       Coordinated by

      Liliana Andrade

      Frédéric Rousseau

      First published 2020 in Great Britain and the United States by ISTE Ltd and John Wiley & Sons, Inc.

      Apart from any fair dealing for the purposes of research or private study, or criticism or review, as permitted under the Copyright, Designs and Patents Act 1988, this publication may only be reproduced, stored or transmitted, in any form or by any means, with the prior permission in writing of the publishers, or in the case of reprographic reproduction in accordance with the terms and licenses issued by the CLA. Enquiries concerning reproduction outside these terms should be sent to the publishers at the undermentioned address:

      ISTE Ltd

      27-37 St George’s Road

      London SW19 4EU

      UK

       www.iste.co.uk

      John Wiley & Sons, Inc.

      111 River Street

      Hoboken, NJ 07030

      USA

       www.wiley.com

      © ISTE Ltd 2020

      The rights of Liliana Andrade and Frédéric Rousseau to be identified as the authors of this work have been asserted by them in accordance with the Copyright, Designs and Patents Act 1988.

      Library of Congress Control Number: 2020940076

      British Library Cataloguing-in-Publication Data

      A CIP record for this book is available from the British Library

      ISBN 978-1-78945-022-4

      ERC code:

      PE6 Computer Science and Informatics

       PE6_1 Computer architecture, pervasive computing, ubiquitous computing

       PE6_10 Web and information systems, database systems, information retrieval and digital libraries, data fusion

      PE7 Systems and Communication Engineering

       PE7_2 Electrical engineering: power components and/or systems

      Foreword

       Ahmed JERRAYA

       Cyber Physical Systems Programs, CEATech, Grenoble, France

      Multi-core and multi-processor SoC (MPSoC) concepts started in the late 1990s, mainly to mitigate the complexity of application-specific integrated circuits (ASICs) and to bring some flexibility. The integration of instruction-set processors into ASIC design aimed both to structure the architecture and to allow for programmability. The concept was adopted for general-purpose CPU and GPU in the second phase. Among the pioneers of MPSoC design, we can list the MPA architecture from ST that used eight specific cores to implement MPEG4 in 1998. This evolved 10 years later to give rise to MPPA, the Kalray’s general-purpose MPSoC architecture. Another pioneer is the emotion engine from Sony that used five cores (two DSP and three RISC) to build the application processor for the PlayStation (PS2). This also evolved and later converged to bring the CELL architecture (developed jointly by Sony, IBM and Toshiba) in 2005. In 2000, Lucent announced Daytona (quad SPARC V8), and in 2001, Philips designed the famous Viper architecture that combined a MIPS architecture and a DSP (Trimedia). In 2004, TI introduced the OMAP architecture that combined an ARM and a DSP. Using MPSoC to build specific architectures is continuing, and almost every SoC produced today is a multi (or many) core architecture. An important evolution took place in 2005 with the ARM MPCore, СКАЧАТЬ