Microprocessor 4. Philippe Darche

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СКАЧАТЬ 2.1b. Classifying instructions in modern MPUs (continuation and end)Figure 2.2a. Classification of the main bit manipulation operationsFigure 2.2b. Classification of the main bit manipulation operations (continuatio...Figure 2.3. Logical left and right shiftsFigure 2.4. Shift arithmetic rightFigure 2.5. Left and right rotationsFigure 2.6. Left and right rotations through carryFigure 2.7. Generic examples of multiple shifts and rotationFigure 2.8. Double shift with a 386Figure 2.9. Field extract and field deposit operationsFigure 2.10. Left shuffle operation (interleaving)Figure 2.11. Right shuffle operation (interleaving)Figure 2.12. Reverse instructions from the Arm® and Thumb® family (n = 64)Figure 2.13. Classifying advanced bit manipulationsFigure 2.14. Field extract and field deposit operations of parallel bitsFigure 2.15. Normal butterfly circuit in n = 8 bits format (a) and associated sw...Figure 2.16. Reverse butterfly circuit in n = 8 bits formatFigure 2.17. Branching instructionsFigure 2.18. Execution paths for a jumpFigure 2.19. Execution steps for a conditional jumpFigure 2.20. Execution paths for a conditional jumpFigure 2.21. Left: result state check; right: direct checkFigure 2.22. Schema for evaluating a calculationFigure 2.23. Condition field from MPU Arm® VL86C010Figure 2.24. Instruction bufferFigure 2.25. Hardware management of a loopFigure 2.26. Functional block diagram showing a hardware loop manager (from Tsao...Figure 2.27. Distribution of operations in a vector instruction in a SIMD struct...

      3 Chapter 3Figure 3.1. Instruction alignment in 32-bit format (from Darche (2012) modified)Figure 3.2. Levels of programming languageFigure 3.3. Hierarchy of protected execution modes from the x86 family from Inte...Figure 3.4. Operating modes of an MPU from IA-323 architecture from Intel® (Inte...Figure 3.5. Virtualization in an applicationFigure 3.6. Hypervision of virtual machinesFigure 3.7. Differences between container (a) and serverless (b) (from Wong (201...Figure 3.8. Hierarchization of the instruction set from x86 architectureFigure 3.9. Backward compatibility of the instruction set architecture by enrich...Figure 3.10. Types of compatibility of a digital systemFigure 3.11. Evolution of the calculating performance (MIPS) of the first MPUs f...Figure 3.12. Development of MPU systems’ performance over time (SPECint)Figure 3.13. Comparison of uniprocessor performances between supercomputers and ...Figure 3.14. Comparing (single-core) MPU performances with DRAM8 performances (f...Figure 3.15. Comparison of performances between computer classes (from Hennessy ...

      4 Chapter 4Figure 4.1. Suggested visual representation of a stack SFigure 4.2. Pseudo-code for stacking (a) and unstacking (b) in the format n = 16...Figure 4.3. Operations of stacking and unstacking for TMS320C31Figure 4.4. Managing an ascending stackFigure 4.5. Classical structure of an execution stack (x86 family from Intel)Figure 4.6. Classic main memory mappingFigure 4.7. Stack register of a mathematical coprocessor in floating point from ...Figure 4.8. Stack in shift-register versionFigure 4.9. Unfolding execution of a program with a call to sub-programFigure 4.10. Subroutine call and return and stack content (x86 architecture)Figure 4.11. Recursive calls and returns from a subroutine (nested calls)Figure 4.12. Recursive calls and returns from a subroutine (nested calls)Figure 4.13. Windowing registers (from Scott (2016))

      5 Chapter 5Figure 5.1. Origins of an interrupt request (Darche 2003)Figure 5.2. Ideal forms of external interrupt requestFigure 5.3. Call and return of a non-nested hardware interruptFigure 5.4. Execution flow of a program during a hardware interrupt requestFigure 5.5. Stages in handling an interruptFigure 5.6. Different sources of external interruptsFigure 5.7. Example of management logic for IT requests (Meinadier 1971, 1988)Figure 5.8. Processing chain for several sources of interrupt sharing a single i...Figure 5.9. Simplified decision organigram for considering a hardware interruptFigure 5.10. Execution organigram of a simple MPU: the MC6802 (Motorola 1984)Figure 5.11. Pre-emptive execution in a system of hierarchized interruptsFigure 5.12. Simplified processing logigram of an interrupt from the IT 8259A co...Figure 5.13. Mechanism of nested hardware interruptsFigure 5.14. Call and return of a non-nested software interrupt (example with MC...Figure 5.15. Call and return of nested software interrupts (example with MC6809)Figure 5.16. Call and return of nested software interrupts (example with MC6809)Figure 5.17. Decision process from MC6809 (simplified organigram without HALT an...Figure 5.18. Processing sequence for interrupt requests from 8086 (Intel 1989)Figure 5.19. Step-by-step execution modes with NMI and normal (Intel 1989)Figure 5.20. Simultaneous software exception and maskable external interrupt int...Figure 5.21. Simultaneous NMI, INTR and division by zero in interaction with ste...Figure 5.22. Processing organigram for interrupts from MC6809 (Motorola 1981, 19...Figure 5.23. Vectorization of the interruptFigure 5.24. External vectorizationFigure 5.25. Two typical implantations of different memory areas of an IT systemFigure 5.26. Proposal for processing flow for many IT requests (Intel 1980)Figure 5.27. Organization of different APICs

      6 ExercisesFigure E2.28. Generation of address signals corresponding to an execution of a s...

      List of Tables

      1 Chapter 1Table 1.1. Possible address combinations in family IA-32Table 1.2. Combined MC6809 addressing modes

      2 Chapter 2Table 2.1. Logical instructions from DEC System-10Table 2.2. Conditional jump instructions for 8086 for whole numbersTable 2.3. Condition codes from the Arm® architecture

      3 Chapter 3Table 3.1. Additional cost in the number of cycles and memory clutter for the MC...Table 3.2. Effective address calculation time (8086)Table 3.3. Arm® architecture execution modesTable 3.4. List of iCOMP benchmarks

      4 Chapter 4Table 4.1. Solutions for managing a stack in main memory

      5 Chapter 5Table 5.1. Maskable and non-maskable interruptsTable 5.2. Categories of interrupt to qualify a double fault in 80386 (Intel 198...Table 5.3. Decision criteria for qualifying a double fault in 80386 (Intel 1986)Table 5.4. Priorities of different interrupts from 8086Table 5.5. Table of 256 interrupt vectors from IA-32 architectureTable 5.6. List of exception codes (ExcCode) for MIPS architecture (Kane 1988; K...Table 5.7. Management options in the case of multiple IT processingTable 5.8. Table summarizing interruptsTable 5.9. Interrupt recovery points for the 80286Table 5.10. Recovery point for ITs for the 80286 (real mode)Table 5.11. Recovery point for ITs for the 80286 (protected mode)Table 5.12a. Suggestion for classification criteria according to Hennessy and Pa...Table 5.12b. Suggestion of classification criteria according to Hennessy and Pat...

      6 AppendixTable A.1a. Hexadecimal values of machine codesTable A.1b. Hexadecimal values of machine codesTable A.2a. Programming aidTable A.2b. Programming aidTable A.2c. Programming aid

      Guide

      1  Cover

      2  Table of Contents

      3  Title page

      4  Copyright

      5  Quotation

      6  Preface

      7  Introduction

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