Microprocessor 4. Philippe Darche

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      Figure 1.26. Flow diagram of the algorithm of an 8-point FFT DIT in base 2

To carry out this inversion of the address bit order, Reverse-Carry Arithmetic (RCA) is used. The sub-set managing the address or AGU (cf. § V3-3.4.4) reverses the direction of the bits retained when an increment is added to the value of an address register. Two processors that implement it are DSP32xx from AT&T and DSP56000 (Motorola 1992). The AGU also implements linear and modulo arithmetic.

      1.2.4.5.3. Linear addressing

      The DSP56000 uses a – perhaps poorly named – address modifier. It makes it possible to jump address at each access with a stored constant memorization in a register. The benefit is easy access to the elements of a complex data structure.

      1.2.4.6. Modes specific to the assembler

      The assembler can offer addressing modes that do not exist in the MPU. Each instruction using them will be replaced by an equivalent logical sequence. One example is symbolic addressing, which facilitates programming of a jump to a specific location in the code marked by a symbolic name called a label (cf. § V5-1.3.3). This mode belongs to assembly language (cf. § V5-1.3), unlike those seen previously in this chapter which belong to machine language. It is used to make a jump to a precise place in the code marked by this symbolic name. One example is MPU MIPS R2000/R3000 (Kane 1988).

      1.2.4.7. Obsolete modes

      The modes studied so far are those that are currently available. Some modes have been abandoned because they are complex or not useful. For example, pagezero and direct paged modes (microprocessor IM6100 from Intersil) with current memory sizes are no longer required. We also mention truncation, which consists of deleting the most significant address bits to adapt to addressing capacity in the storage hierarchy considered (Brooks 1962).

      1.2.4.8. Note

      Sequential execution of instructions in von Neumann architecture (cf. § V1-3.2.2) can be seen as a sequential addressing mode (source: Wikipedia).

      1.2.5. Summary on addressing

Addressing modes have evolved to meet needs in the software industry to improve efficiency of programs and facilitate implementing functionalities of high- level languages as their control structures. It is useful to class addressing modes depending on their content, code or data. Simple code addressing modes are Program Counter (PC)-relative absolute addressings and indirect register addressings. Sequential execution by nop instruction can be seen as an addressing mode. Sample data addressing modes are immediate, (direct) register, implicit and base plus offset modes. Mixed (code/data) modes are direct absolute and indexed, base plus index modes with or without offset (base plus index plus offset), scaled indexed modes, register indirect modes, indirect register modes with auto-increment, indirect memory and PC-relative modes.

      Making the programmer accessible to registers that are not conventional, such as PC and SP, makes it possible to enrich addressing modes. Thus, some modes can be implemented using others, such as, for example, absolute and relative modes with respectively indirect and indexed modes.

      The trend has been towards multiplying addressing modes, making it possible to adapt to complex data structures such as those of high-level languages or application domains such as digital signal processing with its operations such as convolution or correlation. This wealth of modes facilitates the life of the assembly language programmer and makes it possible for the code to be compact during compilation. The counterpart is the complexity of the CU (Control Unit), one of the defects of the CISC approach (this will be covered in a future book by the author on microprocessors). The number of possibilities of machine codes depends on the number of instructions and associated addressing modes. Therefore, MC6809 had 59 instructions and 1,464 machine codes (Motorola 1981, 1983). A reverse tendency was that of reduced instruction set architectures (RISC, this will be covered in a future book by the author on microprocessors).

1.3. Conclusion

      The following chapter focuses on the instruction set for a generic microprocessor by presenting the different instruction families and extensions in this set.