Microprocessor 4. Philippe Darche

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      Figure 1.9. Execution of an instruction using register addressing from one register

      The example below shows an addition in an Arm^® microprocessor, which uses three registers: r0, r1 and r2:

      ADD r0,r1,r2; r0 ← r1 + r2

      Note, a distinction can be made between Data Register Direct Addressing and Address Register Direct Addressing as for MC68000 (cf. § V3-3.1.1).

      1.2.2.2. Implicit register addressing

To simplify the programming, some instructions use one or more registers in an extended or implicit manner. In this addressing mode, also called implicit or implied addressing mode, no operand is specified after the instruction mnemonic (cf. § 2.1). Execution of the instruction involves the reference to operand that is not joined to the operating code. One synonym is implication (Brooks 1962). The instruction format is reduced by it. One example is the dex instruction from MCS6502, which decrements its index register X. The name of this appears in the mnemonic to facilitate programming. Sometimes when the accumulators are used, this mode is called “accumulator addressing”. The example below applied to MC6809. The accumulator B specified by the last letter of the mnemonic receives a value expressed in hexadecimal base.

      LDB #$FA; B ← FA16

      If the name of the registers does not appear in the mnemonic, then only a detailed reading of the technical documentation can specify the name of these registers. In the example below (MC6809), the instruction for multiplication mul (without operands) implicitly uses both implicit accumulator registers A and B and stores the concatenated result in these same registers, and the MSB (Most Significant Byte) is found in accumulator A, which in pseudo-code gives: A:B ← A × B.

      Another example is the instruction from 8086 mul bl, which uses the implicit register A as source and destination operands in the case of multiplication in 8-bit format (ax ← bl × al for this example).

      To generalize, an instruction lacking one or more operands found in a register (an accumulator for example) or in memory uses implicit addressing. We find this mode in machines with a single address called an accumulator or in the extreme case of zero-operand computers also called stack or pushdown-store machine (cf. § V1-2.7.1). By broadening the definition to registers that are not accessible to the programmer, any instruction for its execution uses the PC (Program Counter), which is therefore implicit.

      1.2.3. Memory addressing modes

      It is possible to address the memory in a direct, relative, indirect, indexed or based manner. Combinations of these modes are possible. Other specific modes are then presented.

      1.2.3.1. Direct addressing

Direct or absolute addressing is without doubt the most natural. It can access a memory address location A defined (i.e. arranged immediately) after the instruction code in the operand field (Figure 1.10). It can therefore be considered a constant. The effective address EA is given by the following formula:

      [1.1]

      Figure 1.10. Instruction with direct addressing

      It can be used by jump instruction to branch to a set location in the program. This mode is in fact an indirect mode with auto-incrementation using the PC (Program Counter) as an indirection register (cf. § 1.2.3.3 for indirection).

This mode allows for variations depending on the format of the address provided, the benefit lies in reducing the instruction's memory size. Some manufacturers thus distinguish the short mode from the extended mode, known as long mode, depending on the format of the address A, provided. In the short mode (absolute short, page zero, also known direct at Motorola, a base page (IEEE 1985)) illustrated in Figure 1.11, the address is expressed in a smaller format than that of a microprocessor. The address field may also be smaller than 3 bits, one example being the 8021 microcontroller from Intel or, classically, 8 bits in 8-bit MPUs. Page zero can be seen as a bank of registers (RF for Register File, cf. § V3-3.1.11.1). The MIPS firm speaks of pseudo-direct addressing. Aside from a smaller format, the second benefit lies in decreasing the number of memory accesses to fetch the instruction code and the operand address. It is equivalent to a basic addressing + displacement, as in the IBM System/370 architecture, with a null base address. One example is the MC6802 microprocessor where the address is in byte format, while the format of the MPU address bus is double. This then limits the address space to the interval [00, FF]₁₆, hence the term “absolute short addressing” or “page zero”⁶ (if the size of the memory page is 256 bytes). In the example below, the A register receives the content of memory location 00.

      Figure 1.11. Instruction with an address at page 0

      The concept of page zero addressing has been improved with direct page addressing. The direct page is now movable in a larger memory page. The start of the page is addressed by a specialized register (cf. § V3-3.1.1). We cite MC6809 (a page of 256 bytes in a space of 64 KiB, addressing capacity of the MPU itself, direct page (DP) register), the 65CE02 from Commodore Semiconductor Group or CSG (the same as before except that its addressing capacity is higher, base page register B) and the 65816 from the firm Western Digital Corporation (WDC) with an address over 16 bits in the direct page register D.

A direct addressing is limited in its extent for a given instruction format; there are bits reserved for coding the instruction, which should be subtracted from the bits reserved for the addressing. This limitation can be lifted if the instruction format is not limited (i.e. variable format). With extended addressing, the address belongs to the microprocessor's address space without restriction. The format is that of the address bus. It should be noted that the absolute address can be implemented СКАЧАТЬ