Artificial Intelligence Hardware Design. Albert Chun-Chen Liu

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СКАЧАТЬ processing order.Figure 7.14 Cnvlutin processing order.Figure 7.15 Cnvlutin zero free neuron array format.Figure 7.16 Cnvlutin dispatch.Figure 7.17 Cnvlutin timing comparison [4].Figure 7.18 Cnvlutin power comparison [4].Figure 7.19 Cnvlutin² ineffectual activation skipping.Figure 7.20 Cnvlutin² ineffectual weight skipping.

      8 Chapter 8Figure 8.1 EIE leading nonzero detection network.Figure 8.2 EIE processing element architecture.Figure 8.3 Deep compression weight sharing and quantization.Figure 8.4 Matrix W, vector a and b are interleaved over four processing ele...Figure 8.5 Matrix W layout in compressed sparse column format.Figure 8.6 EIE timing performance comparison [1].Figure 8.7 EIE energy efficient comparison [1].Figure 8.8 Cambricon‐X architecture.Figure 8.9 Cambricon‐X processing element architecture.Figure 8.10 Cambricon‐X sparse compression.Figure 8.11 Cambricon‐X buffer controller architecture.Figure 8.12 Cambricon‐X index module architecture.Figure 8.13 Cambricon‐X direct indexing architecture.Figure 8.14 Cambricon‐X step indexing architecture.Figure 8.15 Cambricon‐X timing performance comparison [4].Figure 8.16 Cambricon‐X energy efficiency comparison [4].Figure 8.17 SCNN convolution.Figure 8.18 SCNN convolution nested loop.Figure 8.19 PT‐IS‐CP‐dense dataflow.Figure 8.20 SCNN architecture.Figure 8.21 SCNN dataflow.Figure 8.22 SCNN weight compression.Figure 8.23 SCNN timing performance comparison [5].Figure 8.24 SCNN energy efficiency comparison [5].Figure 8.25 SeerNet architecture.Figure 8.26 SeerNet Q‐ReLU and Q‐max‐pooling.Figure 8.27 SeerNet quantization.Figure 8.28 SeerNet sparsity‐mask encoding.

      9 Chapter 9Figure 9.1 2.5D interposer architecture.Figure 9.2 3D stacked architecture.Figure 9.3 3D‐IC PDN configuration (pyramid shape).Figure 9.4 PDN – Conventional PDN Manthan geometry.Figure 9.5 Novel PDN X topology.Figure 9.6 3D network bridge.Figure 9.7 Neural network layer multiple nodes connection.Figure 9.8 3D network switch.Figure 9.9 3D network bridge segmentation.Figure 9.10 Multiple‐channel bidirectional high‐speed link.Figure 9.11 Power switch configuration.Figure 9.12 3D neural processing power gating approach.Figure 9.13 3D neural processing clock gating approach.

      Guide

      1  Cover Page

      2  Series Page

      3  Title Page

      4  Copyright Page

      5  Author Biographies

      6  Preface

      7  Acknowledgments

      8  Table of Figures

      9  Table of Contents

      10  Begin Reading

      11  Appendix A Neural Network Topology

      12  Index

      13  Wiley End User License Agreement

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