Digital System Design using FSMs. Peter D. Minns
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Название: Digital System Design using FSMs
Автор: Peter D. Minns
Издательство: John Wiley & Sons Limited
Жанр: Техническая литература
isbn: 9781119782728
isbn:
Note that the states run through from s0 to sn−1, for n states.
As well as containing flip‐flops to uniquely define the individual states of the FSM, there is also combinational logic, which defines the outside world outputs. In addition, the outside world inputs connect to combinational logic, which supplies the flip‐flops’ inputs.
Please turn to Frame 1.4.
Figure 1.3 illustrates the internal architecture for a Mealy FSM.
Figure 1.3 Block diagram of a Mealy state machine structure.
Note the feed forward paths between the outside world inputs and the input to the output decoder.
The figure shows that the FSM has a number of inputs that connect to the next state decoder (combinational) logic. The Q outputs of the memory element flip‐flops connect to the output decoder logic, which in turn connects to the outside world outputs via the output decoder.
The flip‐flop outputs are used as next state inputs to the next state decoder, and it is these that determine the next state that the FSM will move to. Once the FSM has moved to this next state, its flip‐flops acquire a new present state as dictated by the next state decoder.
Note that some of the outside world inputs connect directly to the output decoder logic. This is the main feature of the Mealy type of FSM. This affects the outputs of the FSM.
Please turn to Frame 1.5.
Another architectural form for an FSM is the Moore FSM, as shown in Figure 1.4.
Figure 1.4 Block diagram of a Moore state machine structure.
This FSM differs from the Mealy FSM in that it does not have the feed forward paths.
This type of FSM is very common. Note that the outside world outputs are a function of the flip‐flop outputs only (unlike the Mealy FSM architecture where the outside world outputs are a function of flip‐flop outputs and some outside world inputs).
We will be using both Moore and Mealy FSM in our designs.
Please turn to Frame 1.6.
Complete the following:
A Moore FSM differs to that of a Mealy FSM in that it has…
This means that the Moore FSM outputs depend on…
Whilst the Mealy FSM outputs can depend upon…
If you cannot complete the above sentences, go back and read Frame 1.4 and Frame 1.5.
When you have completed these questions, please go to Frame 1.7.
If we look at the Moore FSM architecture again and remove all of the outside world inputs apart from the clock, and we also remove the output decoding logic, we are left with a very familiar architecture. This is shown in Figure 1.5.
Figure 1.5 Block diagram of a Class C state machine structure.
This architecture is in fact the synchronous counter the reader may have already seen in previous studies. Note that an up/down counter would have the additional outside world input ‘up/down’, which would be used to control the direction of counting.
The flip‐flop outputs in this architecture are used to connect directly to the outside world.
Please move on to Frame 1.8.
Historically, two types of state diagrams have evolved, one for the design of the Mealy FSM the other for the design of the Moore FSM. The two are known as ‘Mealy state diagrams’ and ‘Moore state diagrams’.
These days we use a more general type of state diagram, which can be used to design both the Mealy and Moore type of FSM. This is the type of state diagram we use throughout this book. As you will learn, it allows you to build a lot of ideas into the FSM diagram.
Figure 1.6 shows each state of the FSM and the transitions to and from that state to other states.
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