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Название: Design and Development of Efficient Energy Systems

Автор: Группа авторов

Издательство: John Wiley & Sons Limited

Жанр: Программы

Серия:

isbn: 9781119761792

isbn:

СКАЧАТЬ Figure 2.10, 15;5 compressor made of seven full adders, three half adders, and two 7:3 compressors. The working principle of this compressor is understood as input (X1-X3) inputs applied to the full adder (FP11). (X4-X6) inputs are provided to full adder (FP2), (X7-X9) inputs are given to full adder (FP3), (X10-X12) inputs are given to full adder (FP4), (X13-X15) inputs are given to full adder (FP5), (X16-X18) inputs are given to full adder (FP6) and the last two inputs (X19-X20) are given to half adder (HP1). The sum obtained from this (FP1), (FP2), (FP3), (FP4), (FP5), (FP6), and (HP1) is given to 7:3 compressor (CP1) and carry is given to another 7:3 compressor (CP2). The sum obtained from 7:3 compressor (CP1) is the output Y1of the compressor.

      The output carry1 of 7:3 compressor (CP1) and the sum obtained from 7:3 compressor (CP2) is given to half adder (HP2). The sum which is obtained from half adder (HP2) is taken as output Y2. The carry of half adder (HP2), carry2 of 7:3 compressor (CP1), and carry1 of 7:3 compressor (CP2) given to full adder (FP7). The sum obtained from full adder (FP7) taken as output Y3. The carry of this full adder (FP7) and carry2 of 7:3 compressor (CP2) given to half adder (HP2). The sum obtained from half adder (HP3) is taken as output Y4 and carry is taken as output Y5. Different compressor blocks are integrated to develop the architecture using the Boolean equation.

Schematic illustration of behavioral simulation of 8 by 8 VM.
Device utilization summary
Logic utilizations Used Available Utilization
Slices 418 1672 4%
4 input LUTs 729 17344 4%
Bounded IOBs 67 250 26%

      The case I Input A=8’d136 and B=8’d119 result in multiplier values p=16’h16184.

      Case II Input A=8’d141 and B=8’d124 result in multiplier values p=16’h17484.

      Case III Input A=8’d145 and B=8’d129 result in multiplier values p=16’h18834.

      The performance parameter of 8-bit VM is judged by power consumption, delay, and area report obtained by the cadence RTL compiler. Completed implementation of an 8-bit Vedic multiplier is through the combinatorial block. The usage of the compressor reduces the requirement of resources. As the number of the logic gate but increases the interconnecting wires. Similarly, area requirements to interface multiple compressors significantly enhance the area and delay. In this section area, power and delay are presented due to logical resources and wires.

      2.4.1 Instance Power

Pie chart depicts instance power usage of 16 by 16 VM.

      2.4.2 Net Power