Design and Development of Efficient Energy Systems. Группа авторов

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СКАЧАТЬ high I_ON/I_OFF current ratio. These prefabrication low-power design and analysis can be done on a Visual TCAD device simulator with graphical and programming interfaces that reduce fabrication cost and improve overall throughput.

      Keywords: Low power, junction-less, DGMOSFET, TCAD, leakage current, etc.

1.1 Introduction

The size of semiconductor devices is being continuously reduced and has entered into the nanoscale range. Every two years the number of transistors doubles because the size of the MOSFET is reduced. Reducing the size of the MOSFET reduces the size of the channel, which causes short-channel effects and it increases the leakage current. Reduction in the size of semiconductor devices has given rise to short-channel effects (SCEs). The various SCEs are parasitic capacitances, drain field effect on channel field, degraded subthreshold region of operation, mobility degradation, hot carrier effects, etc. To overcome these effects the devices need to be engineered using different techniques like gate or channel engineering. The cause of the SCEs is when the width of the drain barrier extends into the drain and source region barrier lowering. Many MOSFET structures like DG-MOSFET, GAA (Gate-all-around) MOSFET, TG (Triple-gate) MOSFET, SOI (Silicon-on-insulator) MOSFET, double-step buried-oxide including junction-less properties have been designed to overcome SCEs [1–6].

      MOSFETs are used for analog and RF applications to handle the radio frequency signals that are high in power from devices like televisions, radio transmitters, and amplifiers. MOSFETs are used for biomedical applications [7]. It is used as a biosensor to detect bio-molecules. It is useful in detecting molecules like enzymes, nucleotide, protein and antibodies. Using MOSFETs as a biosensor has benefits over other methods as it has more sensitivity, compatibility, mass production and miniaturization. MOSFET is also used to store memory. It is used in the construction of SRAM cells for storing data. MOSFETs were also adopted by NASA to detect interplanetary magnetic fields and interplanetary plasma. MOSFETs are used in digital applications for switching which prevents DC to flow supply and ground that lead to reduced power consumption and providing high input impedance.

1.2 MOSFET Performance Parameters

      The MOSFET performance mainly depends on ON and OFF state conditions depending on the different applied bias voltage. The performance analysis is categorized as:

      1 a) DC AnalysisIn DC analysis, subthreshold parameters are mainly calculated such as IOFF, DIBL, SS, and threshold voltage (Vth). These parameters can be defined as:i) IOFF: It is OFF-state current when the applied gate voltage (Vgs) is less than the threshold voltage (Vth).ii) Vth: It the required minimum value of the gate voltage to establish channel inversion.iii) Subthreshold Slope (SS): It is one of SCE that can be derived from the equation:(1.1)iv) Drain induced barrier lowering (DIBL): DIBL is another important parameter of SCE which is a measure of threshold voltage variations with the variation in drain voltage for constant drain current. It can be derived from the equation:(1.2)

      2 b) AC analysisAC analysis is dependent on frequency of applied bias voltages. The important ac parameters are:i) Transistor Capacitance (Cg): There are several inherent capacitances such as gate to source, the gate to drain and gate to body capacitances. Transistor capacitances are important for desired switching behavior from OFF to ON state.ii) Transconductance (gm): It is a measure of drain current with the variation in gate voltage for constant drain current. It plays an important role to achieve high value of transistor amplifier gain. It can be derived from the equation:(1.3)

      3 c) Electrostatic CharacteristicsThere are a few other important parameters that also have significant importance of MOSFET behavior during ON/OFF state. Energy band diagram, channel potential, electric field distribution and electron-hole density are important electrostatic properties that need to be analysed while designing any MOSFET architecture.

1.3 Comparison of Existing MOSFET Architectures

Table 1.1 shows a comparison of existing MOSFET structures based on their performance and suitable applications.

1.4 Proposed Heavily Doped Junction-Less Double Gate MOSFET (AJ-DGMOSFET)

An AJ-DGMOSFET shown in Figure 1.1 has top and bottom gates arranged asymmetrically with an overlap region of 10nm. An n+ pocket region is added to the source side with heavy doping of donor atoms. p+ polysilicon is used as gate contact material with Hfas an oxide region of high-k dielectric constant. The body thickness is kept very low (6nm). The gate (L_gate) is 20 nm, with overlap region (L_overlap) of 10 nm. The body thickness (T_silicon) is 6 nm source /drain length (L_source = L_drain) of 8 nm. The oxide thickness (T_oxide) is 1 nm. A thin pocket region (n+ doping) is doped with 1x10²² cm^-3 with channel region II doping (n+ doping) of 1x10¹⁹ cm^-3. Including channel region I + and channel region II, the overall channel length becomes 30 nm.

      The high doping concentration of the source drain region with heavy doping of n+ pocket region improves the ON-state current transistor. The drain region doping is slightly less than the source to achieve a low value of leakage current, therefore enhanced current ratio (I_ON/I_OFF). Here channel length is also dependent on bias condition. In ON-state the effective channel length is equal to the length of overlap region of top and bottom gates. In OFF-state, the effective channel length is the length excluding overlap region between top and bottom gate.

Figure 1.2 shows a comparison between ON-state and OFF-state of the transistor. Different characteristics have been drawn with and without pocket region. The proposed AJ-DGMOSFET with heavily doped pocket region shows better ratio in comparison to AJ-DGMOSFET without a doped pocket region.

Table 1.1 Comparison of existing MOSFET structures.

Ref.	Existing MOSFET structure and methodology	Electrical performance and applications
[2]	Ge pockets are inserted in SOI JLT	Reduces the lattice temperature. The channel length is 20 nm.
[3]	Gate all around junctionless MOSFET with source and drain extension	The highly doped regions have also led to an increase in I-ON current magnitude by 70%.
[4]	Gate engineering using double-gate MOSFET	The sub-threshold slope is decreased by 1.61% and ON/OFF current ratio is increased by 17.08% and DIBL is decreased by 4.52%. The channel length is 20 nm.
[5]	Gate material engineering and drain/source Extensions	Improves the RF and analog performance. The figure of merit is also increased compared to the conventional double-gate junctionless MOSFET. The channel length is 100 nm.
[6]	Inducing source and drain extensions electrically	Suppresses short-channel effects for the channel length less than 50 nm and also suppresses hot electron effects.
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