Liquid Crystal Displays. Ernst Lueder

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СКАЧАТЬ angles in brackets [ ] are shown as projections in the drawing planeFigure 8.6 The angles in the Chevron texturesFigure 8.7 The dependency of layer tilt δ_c on the pretilt α in SSFLCDs with the quasi-bookshelf and Chevron texturesFigure 8.8 The cone with the two stable positions of the molecules rotated by angle δ_c from the plane of the polarizers: (a) Isometric view, (b) side viewFigure 8.9 The effective switching angle β_eff(α) with δ_c(α) in Figure 8.7Figure 8.10 The planar texture chiral nematic displays with the axes of the helixes normal to the glass platesFigure 8.11 Homeotropically aligned molecules and the fingerprint texture of chiral nematic displaysFigure 8.12 The focal conic texture of SSCTDs without and for PSCTDs with the polymer networkFigure 8.13 The spectra of reflected light R and of scattered light S in an SSCTDFigure 8.14 Isocontrast curves of a reflective SSCT displayFigure 8.15 Three (resp. two) stacked reflective chiral nematic displays for the generation of coloursFigure 8.16 Transmittance versus voltage of an inverse mode chiral nematic displayFigure 8.17 The three stable states of a nematic cell with 0°, 360° and 180° twistsFigure 8.18 Grating and alignment of a zenithal bistable deviceFigure 8.19 Switching of the twisted zenithal bistable deviceFigure 8.20 Switching of the monostably anchored device from stable state (a) to stable state (d)

      8 Chapter 9Figure 9.1 The deformed helix ferroelectric LCDFigure 9.2 Variation of the director twist φ dependent on the reduced location z′ on the helix and on the field +E and −EFigure 9.3 The texture of the antiferroelectric and of the ferroelectric LC materialFigure 9.4 The switching characteristics of antiferroelectric LCDs, (a) tilt angle Θ (E); (b) transmittance T (E); (c) the textures depending on EFigure 9.5 The V-shaped switching curve of antiferroelectric LCDs

      9 Chapter 10Figure 10.1 The direct addressing of the seven segments of a digitFigure 10.2 The Passive Matrix LCD (PMLCD) with row and column electrodesFigure 10.3 The Active Matrix addressed LCD (AMLCD) with a TFT as pixel switch

      10 Chapter 11Figure 11.1 The voltage for a directly addressed LCDFigure 11.2 The waveforms for Vc, Vs and Vp of a direct addressed LCDFigure 11.3 The reconfigured addressing of the display in Figure 10.1 into a matrix addressing with only 10 external connections

      11 Chapter 12Figure 12.1 A display with 3 × 2 pixels with the desired video information,<img/> white and <img/> blackFigure 12.2 (a) Waveforms V_r1, V_r2, V_r3 in rows 1, 2 and 3; (b) waveforms V_c1 and V_c2 in column 1 and 2; (c) waveforms at pixels in row 1/column 1 and row 2/column 2Figure 12.3 The selection ratio V_on/V_off in Equation (12.21) as a function of the number N of rowsFigure 12.4 The reversal of polarity for row and column voltages in the addressing scheme without and with offsetFigure 12.5 The generation of the voltage needed for a column driverFigure 12.6 The circuit of a column driver for PM addressingFigure 12.7 A superframe of four frames for the generation of five grey shadesFigure 12.8 Pulse Width Modulation of the signal voltage V_c for the generation of grey shadesFigure 12.9 The various matrix architectures for PM-addressed LCDs: (a) and (b) depict modifications of the basic architecture; (c), (d) and (e) show modifications of the dual scan schemeFigure 12.10 The phenomenon of ‘frame response’ in fast LCDsFigure 12.11 The Walsh functions of order 1 to 32Figure 12.12 The row voltage S in Equation (12.43) and the column voltage G_max in Equation (12.46) for N = 256 as a function of L < N rows addressed at a timeFigure 12.13 Probability for column voltage levels as a function of column voltage for L = 4, 32, 256 rows addressed at a timeFigure 12.14 Waveform of a column voltage with 256 time intervals and 32 lines selected at a timeFigure 12.15 Block diagram for row and column drivers of an MLA-LCDFigure 12.16 The decreased levels of row and column voltages for PM addressingFigure 12.17 The reduced transmission at the pixel voltage V_th,V_sat and V_on > V_sat for N′ < NFigure 12.18 Dependence of contrast on frame frequency and on the number L of lines addressed at a timeFigure 12.19 Generation of full-interval PHM grey shades for a single row at a time addressed LCDFigure 12.20 Generation of full-interval PHM grey shade in an MLA-LCDFigure 12.21 Hardware for the generation of row and column voltages for pulse height modulated displaysFigure 12.22 The generation of column voltages including the virtual row by correlation for PHM displaysFigure 12.23 Change of the dielectric constants ε_|| and ε_┴ with frequencyFigure 12.24 The high-frequency voltage versus the low-frequency voltage for a 10 percent and a 90 percent optic transmission in a two frequency driving scheme

      12 Chapter 13Figure 13.1 The hysteresis of the electro-optic response of an FLCD with intensity I versus pulse area AFigure 13.2 Switching thresholds of pulse duration τ_th versus pulse amplitude V_th of FLCDsFigure 13.3 The addressing of FLCDs with the V − τ_min schemeFigure 13.4 The addressing of FLCDs with the Harada scheme with (a) two time slots and (b) four time slots per pixel informationFigure 13.5 The addressing of FLCDs with a

time slot schemeFigure 13.6 The depolarization field E_dep and the ionic field E_ion during switching of an FLCDFigure 13.7 Contrast versus duration of addressing impulse as switching window for (a) low P_s FLCDs and (b) higher P_s FLCDsFigure 13.8 The reflectivity of a cholesteric display versus the applied pixel voltage (a) if the voltage is maintained at the pixel, and (b) if the voltage is applied and then switched offFigure 13.9 Reflectivity and pixel voltage of a cholesteric display versus switching timeFigure 13.10 An example for passive matrix addressing of a cholesteric displayFigure 13.11 The five-phase drive scheme for cholesteric displaysFigure 13.12 The switching of chiral nematic displays with five phases in the drive scheme, p: preparation phase; pp: post-preparation phase; s: selection phase; ps: post-selection phase; e: evolution phase; pe: post-evolution (only relaxation, no action needed)

      13 Chapter 14Figure 14.1 (a) The symbol for a TFT; (b) cross-section of a bottom-gate TFT; (c) cross-section of a top-gate TFTFigure 14.2 (a) Output characteristics of a TFT; (b) input characteristics of a TFT; (c) input characteristics of a TFT with

the ordinateFigure 14.3 Measured (full line) and ideal (dashed line) input characteristics of a TFT with logarithmic ordinateFigure 14.4 The TFT and its environment in a pixel for charging of C_LC (a) to a positive voltage and (b) to a negative voltageFigure 14.5 The gate impulses and their effect on the pixel voltage V_pFigure 14.6 The TFT addressing with a compensation impulseFigure 14.7 The TFT in a pixel with voltages, currents and parasitic capacitancesFigure 14.8 Gate pulses for diminished crosstalk (a) with trapezoidal and (b) with rounded wave formFigure 14.9 The voltage-dependent capacitance of liquid crystalsFigure 14.10 The measured logarithmic input characteristics of an a-Si-TFT with the off-currentsFigure 14.11 The shift of V_th during bias temperature stress testsFigure 14.12 Example for one stage of a shift register for the rows of an AMLCDFigure 14.13 A video driver of an AMLCDFigure 14.14 Block diagram for block parallel video drivers for an AMLCDFigure 14.15 Addressing of an AMLCD with half the number of video driversFigure 14.16 Recycling of charge by closing the switches by the control signal CRFigure 14.17 (a) Blocks of pixels with the same sign of the voltage V_LC; (b) addressing of a line during two row address times. Reproduced from Nishimura et al., 1998 with permission of John Wiley & Sons.Figure 14.18 Introduction of a second line with the same information as the previous lineFigure 14.19 The introduction of an additional line if the capacitor C_s in Figure 14.18 is connected to the gate lineFigure 14.20 The introduction of an additional dot in an LCDFigure 14.21 (a) The entire addressing system; (b) γ-correctionFigure 14.22 (a) Basic pixel layout of an AMLCD; (b) pixel layout with storage capacitor along the edges of the ITO-electrode; (c) cross-section along the line A–A′ in Figure 14.22(b)Figure 14.23 Cross-section of a pixel with an additional black matrix on the active matrix plateFigure 14.24 Pixel with the storage capacitor underneath the pixel electrodeFigure 14.25 A pixel with C_s СКАЧАТЬ